Development of a Compact FPGA-Based ACARS System

Abstract

The Aircraft Communication Addressing and Reporting System (ACARS) is a critical component in aircraft communication, facilitating the transmission of identity information between aircraft and ground stations primarily through radio communications. Traditional ACARS systems employ two primary methods for signal processing. The first method involves demodulating the baseband signal using analog techniques followed by decoding with a PC. This approach incurs significant costs, requires multiple frequency conversions which complicate circuit designs and makes debugging challenging. The second method utilizes an Analog-to-Digital Converter (ADC) to sample the analog intermediate frequency (IF) signal, which is then processed digitally. This approach, however, consumes substantial resources in the subsequent processing units, placing considerable strain on the capabilities of the digital signal processors involved.Digital Down Conversion (DDC) is a pivotal technology in communication detection that simplifies this process. DDC shifts the spectrum to reduce or eliminate the carrier frequency of the signal, then utilizes a decimation filter to refine the signal and align it with the requirements of the receiving system. DDC is extensively utilized in software-defined radio and ultra-wideband radar systems. The process begins with the
digital IF signal passing through a mixer that includes two multipliers. A digital control oscillator generates two orthogonal local oscillator signals that are used to produce the Q and I signals through multiplication. Subsequently, the digital baseband signal is output through a decimation filter, effectively reducing the data rate and streamlining the signal processing chain